Conditional Capturing System for Low Power Clock Distribution Networks

Low-power design is becoming a crucial design objective due to the growing demand on portable applications and increasing difficulties in cooling and heat removal. A clock distribution network (CDN) delivers the clock signal which act as a reference to all sequential elements in the synchronous systems. The clock distribution network consumes a considerable amount of power in electronic devices. The proposed conditional capturing method for clock distribution using current is used to distribute a global clock. Further a pulsed logic is adapted to reduce the power consumption. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals. When the CMPFFE is combined with pulsed logic, the design results in lower average power compared to traditional voltage mode clocks. Keywords— CMPFFE, current mode, low power clock distribution, pulse logic, skew.